Samsung Electronics announced that its 2nm process (SF2Z), which will be launched in 2027, will feature innovative backside Power supply (BSPDN) technology, which is expected to increase performance by 8%, power efficiency by 15%, and reduce chip area by 17%. This is the first time that Samsung has disclosed specific performance improvement data of BSPDN technology, marking a major breakthrough in semiconductor technology.

Compared to traditional positive power supply networks (FSPDN), BSPDN significantly improves the buck problem and reduces signal interference by optimizing the power supply layout. As chip components become increasingly dense, BSPDN acts as a "unplugging" for the chip, moving the power system to the back, not only improving performance, but also reducing power consumption and cost.

In addition, Samsung also revealed the progress of the second-generation 2-nanometer process (SF2P), aiming for mass production in 2026, which will increase performance by 12%, reduce power consumption by 25%, and reduce area by 8% compared to the first-generation SF2.

Since 2022, Samsung has introduced a wraparound gate (GAA) structure to further reduce VDD and improve power efficiency. The VDD of the GAA structure is only 0.58, which is much lower than FinFET and planar structures, showing its great potential for improving energy efficiency. Samsung's competitors TSMC and Intel are also planning to adopt GAA structures in 2-nanometer processes.

This series of technological innovations not only demonstrated Samsung's leading position in the semiconductor field, but also injected new impetus into the future development of the global technology industry.

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